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--- dio_tester_and_breakout [2019/02/24 22:33] – tell
+++ dio_tester_and_breakout [2019/10/07 23:16] (current) – [Revision 2: Jan 2019] tell
@@ Line 63: / Line 63: @@
 ====== Revision 2: Jan 2019 ======
-We made three minor changes to this board design for the 2019 competition season.
+We made three minor changes to this board design for the 2019 competition season.\\
+{{ :diotester-2019s.jpg?300|}}
   * add the text "2019 season" to the back of the board, to help identify which are legal for this season, and which were the 2018 prototypes.  This will be handy next year too: boards built in previous years are fair game for off-robot testing and practice robots, but not legal for competition.
   * add two tiny mounting holes.  To avoid enlarging the board, these holes only accept #2 bolts.  nylon hardware is recommended, as they're quite close to components
   * add silkscreen labeling the three signals on the connectors "ground", "signal", and "+" power.
+This version of the board design is https://oshpark.com/projects/SlhiHbwO
 ====== Proposed Revision 3: Feb 2019 ======
@@ Line 79: / Line 82: @@
 We might build this one, or might build a separate logic gate board.  or both.
+One limitation of the schematic above is that while the inverted outputs can be wire-ORed and not affect the on-board status LED, wire-ORing the inputs would cause all of the LEDs to light if any input was low.  A more elaborate, buffered design would allow either true or inverted output to be wire-ORed, while still giving a useful status of the input.